// *********************************************************************************
// Project Name : zkx2024
// Author       : Glqu
// Email        : QGL_MAX@163.com
// Create Time  : 2024-05-02
// File Name    : WRADDR_GEN_DECODER.v
// Module Name  : decoder
// Called By    :
// Abstract     :
//
// 
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2024-05-02    Macro           1.0                     Original
//  
// *********************************************************************************
module wr_addr_decoder(
    input [17:0] ADDR,
    output reg [4:0] SRAM_NUM,
    output reg [12:0] SRAM_ADDR
    );

    logic [4:0] SRAM_MUX;
    assign SRAM_NUM=SRAM_MUX;
    always@(*) begin
        if(ADDR<8192)begin
            SRAM_MUX=5'd0;
            SRAM_ADDR=ADDR;
            end
        else if(ADDR>=8192&&ADDR<16384)begin
            SRAM_MUX=5'd1;
            SRAM_ADDR=ADDR-8192;
            end
        else if(ADDR>=16384&&ADDR<24576)begin
            SRAM_MUX=5'd2;
            SRAM_ADDR=ADDR-16384;
            end
        else if(ADDR>=24576&&ADDR<32768)begin
            SRAM_MUX=5'd3;
            SRAM_ADDR=ADDR-24576;
            end
        else if(ADDR>=32768&&ADDR<40960)begin
            SRAM_MUX=5'd4;
            SRAM_ADDR=ADDR-32768;
            end
        else if(ADDR>=40960&&ADDR<49152)begin
            SRAM_MUX=5'd5;
            SRAM_ADDR=ADDR-40960;
            end
        else if(ADDR>=49152&&ADDR<57344)begin
            SRAM_MUX=5'd6;
            SRAM_ADDR=ADDR-49152;
            end
        else if(ADDR>=57344&&ADDR<65536)begin
            SRAM_MUX=5'd7;
            SRAM_ADDR=ADDR-57344;
            end
        else if(ADDR>=65536&&ADDR<73728)begin
            SRAM_MUX=5'd8;
            SRAM_ADDR=ADDR-65536;
            end
        else if(ADDR>=73728&&ADDR<81920)begin
            SRAM_MUX=5'd9;
            SRAM_ADDR=ADDR-73728;
            end
        else if(ADDR>=81920&&ADDR<90112)begin
            SRAM_MUX=5'd10;
            SRAM_ADDR=ADDR-81920;
            end
        else if(ADDR>=90112&&ADDR<98304)begin
            SRAM_MUX=5'd11;
            SRAM_ADDR=ADDR-90112;
            end
        else if(ADDR>=98304&&ADDR<106496)begin
            SRAM_MUX=5'd12;
            SRAM_ADDR=ADDR-98304;
            end
        else if(ADDR>=106496&&ADDR<114688)begin
            SRAM_MUX=5'd13;
            SRAM_ADDR=ADDR-106496;
            end
        else if(ADDR>=114688&&ADDR<122800)begin
            SRAM_MUX=5'd14;
            SRAM_ADDR=ADDR-114688;
            end
        else if(ADDR>=122800&&ADDR<131072)begin
            SRAM_MUX=5'd15;
            SRAM_ADDR=ADDR-122800;
            end
        else if(ADDR>=131072&&ADDR<139264)begin
            SRAM_MUX=5'd16;
            SRAM_ADDR=ADDR-131072;
            end
        else if(ADDR>=139264&&ADDR<147456)begin
            SRAM_MUX=5'd17;
            SRAM_ADDR=ADDR-139264;
            end
        else if(ADDR>=147456&&ADDR<155648)begin
            SRAM_MUX=5'd18;
            SRAM_ADDR=ADDR-147456;
            end
        else if(ADDR>=155648&&ADDR<163840)begin
            SRAM_MUX=5'd19;
            SRAM_ADDR=ADDR-155648;
            end
        else if(ADDR>=163840&&ADDR<172032)begin
            SRAM_MUX=5'd20;
            SRAM_ADDR=ADDR-163840;
            end
        else if(ADDR>=172032&&ADDR<180224)begin
            SRAM_MUX=5'd21;
            SRAM_ADDR=ADDR-172032;
            end
        else if(ADDR>=180224&&ADDR<188416)begin
            SRAM_MUX=5'd22;
            SRAM_ADDR=ADDR-180224;
            end
        else if(ADDR>=188416&&ADDR<196608)begin
            SRAM_MUX=5'd23;
            SRAM_ADDR=ADDR-188416;
            end
        else if(ADDR>=196608&&ADDR<204800)begin
            SRAM_MUX=5'd24;
            SRAM_ADDR=ADDR-196608;
            end
        else if(ADDR>=204800&&ADDR<212992)begin
            SRAM_MUX=5'd25;
            SRAM_ADDR=ADDR-204800;
            end
        else if(ADDR>=212992&&ADDR<221184)begin
            SRAM_MUX=5'd26;
            SRAM_ADDR=ADDR-212992;
            end
        else if(ADDR>=221184&&ADDR<229376)begin
            SRAM_MUX=5'd27;
            SRAM_ADDR=ADDR-221184;
            end
        else if(ADDR>=229376&&ADDR<237568)begin
            SRAM_MUX=5'd28;
            SRAM_ADDR=ADDR-229376;
            end
        else if(ADDR>=237568&&ADDR<245760)begin
            SRAM_MUX=5'd29;
            SRAM_ADDR=ADDR-237568;
            end
        else if(ADDR>=245760&&ADDR<253952)begin
            SRAM_MUX=5'd30;
            SRAM_ADDR=ADDR-245760;
            end
        else if(ADDR>=253952)begin
            SRAM_MUX=5'd31;
            SRAM_ADDR=ADDR-253952;
            end
        else begin
            SRAM_MUX=5'd0;
            SRAM_ADDR='d0;
            end
    end
endmodule
